Kod: Zaznacz cały
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity registers is
port(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
SEL : in STD_LOGIC;
WR : in STD_LOGIC;
ADDR : in STD_LOGIC_VECTOR(2 downto 0);
Data_In : in STD_LOGIC_VECTOR(7 downto 0);
Data_Out : out STD_LOGIC_VECTOR(7 downto 0);
BUSY : in STD_LOGIC;
Rx_Data : in STD_LOGIC_VECTOR(7 downto 0);
Rx_Ready : in STD_LOGIC;
Data_Send : out STD_LOGIC_VECTOR(7 downto 0);
Rx_Req : out STD_LOGIC;
Tx_Req : out STD_LOGIC
);
end registers;
--}} End of automatically maintained section
architecture registers of registers is
type REGS is array (0 to 7) of std_logic_vector(7 downto 0);
signal Registers : REGS;
signal RxAck : std_logic;
signal TiP : std_logic;
signal EN : std_logic;
signal STA : std_logic;
signal STO : std_logic;
signal RxD : std_logic;
signal TxR : std_logic;
signal ACK : std_logic;
begin
process(SEL, ADDR, Registers)
begin
case ADDR is
when "000" => Data_Out <= Registers(0);-- Status Register
when "001" => Data_Out <= Registers(1);-- Control/Command Register
when "010" => Data_Out <= Registers(2);-- Output Data Register
when "011" => Data_Out <= Registers(3);-- Input Data Register
when "100" => Data_Out <= Registers(4);
when "101" => Data_Out <= Registers(5);
when "110" => Data_Out <= Registers(6);
when "111" => Data_Out <= Registers(7);
when others => null;
end case;
end process;
-- Status Register
process(RST, CLK, BUSY)
begin
if RST='1' then
Registers(0)<=(others=>'0');
elsif CLK'event and CLK='1' then
Registers(0)(7) <= BUSY;
Registers(0)(6) <= RxAck; -- Received acknowledge from slave
Registers(0)(5) <= TiP; -- Transfer in progress
end if;
end process;
-- Control.Command Register
process (RST, CLK, EN, STA, STO, RxD, TxR, ACK)
begin
if RST = '1' then
Registers(1) <= (others=>'0');
elsif CLK'event and CLK= '1' then
Registers(1)(7) <= EN;
Registers(1)(6) <= STA;
Registers(1)(5) <= STO;
Registers(1)(4) <= RxD;
Registers(1)(3) <= TxR;
Registers(1)(2) <= ACK;
end if;
end process;
-- Output Data Register
process(RST, CLK, SEL, WR, ADDR)
begin
if RST = '1' then
Registers(2) <= (others=>'0');
Data_Send <= (others=>'0');
Tx_Req <= '0';
elsif CLK'event and CLK = '1' then
if SEL = '1' and WR = '1' and ADDR = "010" then
Tx_Req <= '1';
Registers(2) <= Data_In; -- z magistrali
Data_Send <= Data_In;
else
Tx_Req<='0';
end if;
end if;
end process;
-- Input Data Register
process(RST, CLK, Rx_Data)
begin
if RST = '1' then
Registers(3) <= (others=>'0');
Rx_Req <= '0';
elsif CLK'event and CLK='1' then
if Rx_Ready='1' then
Registers(3) <= Rx_Data; -- odbior
end if;
if SEL = '1' and WR = '1' and ADDR = "011" then
Rx_Req <= '1';
Registers(3) <= (others=>'0');
else
Rx_Req<='0';
end if;
end if;
end process;
end registers;
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